Getting Started

Vogls is a Verilog simulator that aims to fast, flexible and embeddable into tools. It was specifically built to create tools for design stage side-channel analysis.

⚠️ Warning

Although we use Vogls for our own research, it is still very much alpha software. We hope to develop in the open and collaborate to resolve bugs and implement missing features.

It can be used as a Rust library, Python library or as a command-line interface application.

To see an example of how it is used as a Rust library, look at the source code of Pipeline Explorer.

To see an example of how it is used as a Python library, look at the documentation.

To use it as a command-line application, install it by following the README and use the provided vogls binary.

Comparison to other tools

Vogls simulation is Verilog compliant but tunable to specific use-cases.

By default, Vogls interprets your design, but it can also compile your Verilog to native code. See Compile vs. Bytecode for more information.

By default, Vogls uses two-value logic for wires and registers, but it can also use four-value logic. See Two-value vs. Four-value logic for more information.

Icarus Verilog

Icarus Verilog is the closest to Vogls in terms of simulation model. It also implements Verilg simulation semantics, but does not provide a native code execution strategy and always uses four-value logic.

Icarus Verilog is more mature, better tested and likely what designs are tested against. However, it is relatively slow and difficult to embed. We use Icarus Verilog as a reference simulator for the Verilog semantics. However, do note that Verilog simulation semantics has race conditions, so Vogls and Icarus Verilog might not always agree.

Verilator

Verilator compiles a subset of (System)Verilog to C++. This allows for very fast simulation performance, but creates long compilation times and may not be usable for full-timing simulations.

Verilator is generally a better option than Vogls if you mostly care about cycle-accurate simulation performance and don't need to use it in another tool.

Compile vs. Bytecode

Vogls transforms Verilog into its intermediate representation called the Vogls Intermediate Representation (VIR). This representation can then be converted into a format that is suited for bytecode evaluation (default) or native code (using the -C) flag. The following is a pros and cons table.

Two-value vs. Four-value logic

Traditional Verilog uses four-value logic which, apart from logical low 0 and logical high 1, includes unknown X and high-impedance Z states. Certain Verilog designs rely on this for simulation, but most designs can run without these two extra states. Two value logic can be a lot faster and less memory consuming. Therefore, Vogls, by default, utilizes two-value logic for nets and registers. This means that for two-value logic mode:

• Each net or register gets initialized to 0 (instead of X).
• When a net or register is assigned to X or Z, it gets converted to a 0.

Note that even in two-value logic mode, X and Z can still exist in intermediate variables. This allows Verilog constructs like casex to still work.

If you want full four-value logic for nets and registers, you can use the -F flag.

Vogls Intermediate Representation

Vogls translates (i.e. lowers) all Verilog to Vogls Intermediate Representation (VIR).

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Optimizations

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Fuse Signals

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Non-Temporal Optimizations

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