Getting Started

Vogls is a Verilog simulator that aims to fast, flexible and embeddable into tools. It was specifically built to create tools for design stage side-channel analysis.

⚠️ Warning

Although we use Vogls for our own research, it is still very much alpha software. We hope to develop in the open and collaborate to resolve bugs and implement missing features.

It can be used as a Rust library, Python library or as a command-line interface application.

To see an example of how it is used as a Rust library, look at the source code of Pipeline Explorer.

To see an example of how it is used as a Python library, look at the documentation.

To use it as a command-line application, install it by following the README and use the provided vogls binary.